Power supply noise in integrated circuits (ICs) (wherein the terms “IC,” “chips,” “semiconductor chips” are used synonymously throughout this specification) has emerged as a critical issue, particularly in sub-100 nanometer (nm) technology. Power supply noise causes fluctuations in the voltage differences between power supply and ground rails within ICs resulting in unpredictable timing violations or logical event failures. Certain design flows that manage power supply noise rely on power analysis tools based on highly capable, fast transistor-level or abstracted gate-level simulations. How accurately such simulations can predict noises in terms of amplitudes, timings, and locations within a circuit, however, is largely unknown to designers. On-chip measurements of power supply and ground noise waveforms within ICs can provide valuable knowledge for establishing reliable design guides of power supply systems.
Chip designs are becoming increasingly complex as the number of devices implemented on a single chip are increasing. For example, IC designs commonly implement multi-core processors and system-on-chip (SoC) packages. Power supply noise can significantly alter the performance of these ICs. For instance, parasitic effects, such as interconnect resistance, increasingly impact the performance of ICs as technology sizes shrink. Parasitic effects have greatly increased design complexity due to ad hoc work arounds.
Power supply integrity is an important consideration for achieving higher performance of ICs. Degradation of the power integrity causes a voltage droop, which in turn causes unpredictable timing violations or logical event failures. As higher performing ICs are operating in ever lower power thresholds, highly-accurate analysis of a chip's power supply network is desired to improve power integrity.
One type of power supply noise is voltage droop. Transistors in the IC switch on and off millions of times each second. Turning on many transistors simultaneously uses a significant amount of current. When a large current is drawn from the power source, the voltage of the power source falls. This “voltage droop” occurs momentarily until the power source compensates or some of the transistors turn off. A droop of only tenths of a volt can have drastic effects on the operation of transistors in the IC. Monitoring the voltage droop is desirable because effects of voltage droop may be compensated for to prevent a negative impact on IC performance.
Various techniques for monitoring or measuring power supply noise, such as voltage droop, have been developed. Conventionally, these techniques have been analog in nature. That is, the techniques generally require use of analog circuits such as op-amps.
Other proposed measurement techniques are off-chip techniques that employ measurement logic implemented external to the chip. Such measurement techniques that are undesirable because of their inaccuracy. For example, potential changes or additional capacitances introduced by coupling the off-chip measurement circuitry to the portions of the chip being measured may alter the measurement.
One conventional on-chip technique employs a ring oscillator for measuring power supply noise. Ring oscillator speed varies with IC conditions, but the ring oscillator is unable to detect whether the change is due to voltage variation or some other IC condition, such as temperature variation.